The present invention relates to a method for manufacturing a semiconductor device and more specifically relates to a plasma etching technique for a material to be etched.
In recent years, to achieve high-integration and high-speed semiconductor devices, pattern size reduction using techniques such as self-aligned double patterning (SADP) and self-aligned quadruple patterning (SAQP) has progressed at an accelerated pace in a mask forming method. Also, a structure of a transistor is changing from a conventional planar type structure to a fin field effect transistor (Fin FET, hereinbelow referred to as a Fin FET) structure, which is a 3D structure and is a more complicated structure.
As a result, a higher-aspect-ratio device is developed as the device generation is advanced, and a higher-level etching technique has been required. Especially, in a process of etching a trench in silicon for forming a Fin FET gate and a process of etching a dummy gate interconnection in Poly-Si formed to straddle the Fin FET gate, it is difficult to achieve vertical etching due to the high-aspect-ratio structure.
Etchant causing a chemical reaction is difficult to go into a small space between patterns of the high-aspect-ratio structure, and etching is difficult to proceed. Thus, a tapered or footing profile appears, which causes a problem in which an etching stop occurs. To avoid the problem, etching conditions are adjusted to prevent etching from stopping by increasing the flow rate of process gas or adding a small amount of fluorine-containing gas or the like as gas causing a more highly-volatile reaction, for example.
However, since the amount of a reaction product is small as well in the small space, a sufficient sidewall protection film generated by adhesion of the reaction product cannot be formed. Thus, as the etching proceeds, a side-etching profile is generated at a part directly under a mask. As a measure for this problem, a method for inserting a step of oxygen plasma in the middle of the etching to repeat protection of the sidewall and etching is proposed as described in JP-H06-65214-B2, for example.
There is an alternative method, in which the output of RF bias to be applied to wafer is increased to strengthen an ion sputtering effect, accelerate progression of etching in the small space between patterns, increase the amount of the reaction product, and protect the sidewall.